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| CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 (R) PSoC Mixed-Signal Array Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Low power at high speed 2.4V to 5.25V Operating Voltage Operating Voltages Down to 1.0V using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) 4 Analog Type "E" PSoC Blocks provide: * 2 Comparators with DAC Refs * Single or Dual 8-Bit 28 Channel ADC 4 Digital PSoC Blocks provide: * 8 to 32-Bit Timers, Counters, and PWMs * CRC and PRS Modules * Full-Duplex UART, SPITM Master or Slave * Connectable to All GPIO Pins Complex Peripherals by Combining Blocks Flexible On-Chip Memory 8K Flash Program Storage 50,000 Erase/Write Cycles 512 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator Internal Oscillator for Watchdog and Sleep Programmable Pin Configurations 25 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Up to 8 Analog Inputs on GPIO Configurable Interrupt on All GPIO Versatile Analog Mux Common Internal Analog Bus Simultaneous Connection of IO Combinations Capacitive Sensing Application Capability Additional System Resources 2 I CTM Master, Slave and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Block Diagram Cypress Semiconductor Corporation Document Number: 38-12025 Rev. *M * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 18, 2008 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 PSoC(R) Functional Overview The PSoC(R) family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture enables the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture, shown in Figure 1, consists of four main areas: the Core, the System Resources, the Digital System, and the Analog System. Configurable global bus resources allow combining all the device resources into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects. The Digital System The Digital System consists of 4 digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include the following. PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Pseudo Random Sequence Generators (8 to 32 bit) The PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. System Resources provide the following additional capabilities: The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 4. Figure 1. Digital System Block Diagram Port 3 Port 1 Port 2 Port 0 Digital clocks to increase the flexibility of the PSoC mixed-signal arrays. I2C functionality to implement an I2C master and slave. An internal voltage reference, MultiMaster, that provides an absolute value of 1.3V to a number of PSoC subsystems. A switch mode pump (SMP) that generates normal operating voltages off a single battery cell. Various system resets supported by the M8C. Digital Clocks FromCore To System Bus ToAnalog System DIGITAL SYSTEM Digital PSoC Block Array Row 0 DBB00 DBB01 DCB02 Row Input Configuration The Digital System consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIO through a series of global buses that can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. The Analog System consists of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. 8 8 4 DCB03 4 Row Output Configuration 8 8 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Document Number: 38-12025 Rev. *M Page 2 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 The Analog System The Analog System consists of 4 configurable blocks that allow the creation of complex analog signal flows. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are: The Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins may be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: Analog-to-digital converters (single or dual, with 8-bit resolution) Pin-to-pin comparator Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference 1.3V reference (as a System Resource) Track pad, finger sensing. Chip-wide mux that allows analog input from any IO pin. Crosspoint connection between any IO pin combinations. In most PSoC devices, analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The CY8C21x34 devices provide limited functionality Type "E" analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Mixed-Signal Array Technical Reference Manual for detailed information on the CY8C21x34's Type E analog blocks. Figure 2. Analog System Block Diagram When designing capacitive sensing applications, refer to the signal-to-noise system level requirement found in Application Note AN2403 on the Cypress web site at http://www.cypress.com. Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow. Array Input Configuration Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. Versatile analog multiplexer system. ACI0[1:0] A IO ll X X X X ACI1[1:0] ACOL1MUX Analog MuxBus X Array ACE00 ASE10 ACE01 ASE11 Document Number: 38-12025 Rev. *M Page 3 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted in this table. Table 1. PSoC Device Characteristics Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Digital IO PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 Flash Size 32K 16K contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://www.cypress.com/techtrain. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. up to 4 64 up to 2 44 56 1 16 8 4 4 4 4 0 12 12 48 12 28 8 28 4 4 2 2 0 0 0 4 4 2 2 2 2 0 12 12 6 6 4a 4a 3b 2K 256 16K Bytes 1K 256 4K Bytes 512 8K Bytes 256 4K Bytes 512 8K Bytes CY8C24x23A up to 1 24 CY8C21x34 CY8C21x23 CY8C20x34 up to 1 28 16 1 Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support. Application Notes A long list of application notes can assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default. up to 0 28 a. Limited analog functionality. b. Two analog blocks and one CapSense. Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information with detailed programming information, refer the PSoC Mixed-Signal Array Technical Reference Manual available at http://www.cypress.com/psoc. For up-to-date Ordering, Packaging, and Electrical Specification information, refer the latest PSoC device data sheets at http://www.cypress.com. Development Tools PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (See Figure 3 on page 5) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store Document Number: 38-12025 Rev. *M Page 4 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Figure 3. PSoC Designer Subsystems Design Browser The Design Browser enables users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the seamless merging of the assembly code with C code. The link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler that supports the PSoC family of devices is available. Even if you have never worked in the C language before, the product quickly helps you create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. PSoC Designer Software Subsystems Device Editor The device editor subsystem enables the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows changing configurations at run time. PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. After the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 38-12025 Rev. *M Page 5 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware and software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other uncommon peripherals, such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You can pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you must also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Figure 4. User Module and Source Code Development Flows Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and enables you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Document Number: 38-12025 Rev. *M Page 6 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 2. Acronyms Used Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC(R) PWM SC SLIMO SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Units of Measure A units of measure table is located in the Electrical Specifications section. Table 2 on page 7 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. Document Number: 38-12025 Rev. *M Page 7 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Pin Information The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a "P") is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 16-Pin Part Pinout Figure 5. CY8C21234 16-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] SMP Vss M,I2C SCL,P1[1] Vss 1 2 3 4 5 6 7 8 SOIC 16 15 14 13 12 11 10 9 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P1[4], EXTCLK, M P1[2],M P1[0], I2C SDA, M Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Digital IO IO IO IO Power Power IO Power IO IO IO IO IO IO IO Power Type Analog I, M I, M I, M I, M Name P0[7] P0[5] P0[3] P0[1] SMP Vss P1[1] Vss P1[0] P1[2] P1[4] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Analog column mux input, integrating input. Switch Mode Pump (SMP) connection to required external components. Ground connection. I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. M M M M I, M I, M I, M I, M LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. Document Number: 38-12025 Rev. *M Page 8 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 20-Pin Part Pinout Figure 6. CY8C21334 20-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] Vss M,I2C SCL,P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL,P1[1] Vss 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA, M Table 4. Pin Definitions - CY8C21334 20-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type Digital Analog IO I, M IO I, M IO I, M IO I, M Power IO M IO M IO M IO M Power IO M IO M IO M IO M Input IO I, M IO I, M IO I, M IO I, M Power Name P0[7] P0[5] P0[3] P0[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Analog column mux input, integrating input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. Document Number: 38-12025 Rev. *M Page 9 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 28-Pin Part Pinout Figure 7. CY8C21534 28-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M,P2[7] M,P2[5] M, P2[3] M, P2[1] Vss M,I2C SCL,P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL,P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M P2[4],M P2[2],M P2[0],M XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA, M Table 5. Pin Definitions - CY8C21534 28-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital IO IO IO IO IO IO IO IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO Power Analog I, M I, M I, M I, M M M I, M I, M M M M M M M M M I, M I, M M M I, M I, M I, M I, M Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output, integrating input. Analog column mux input, integrating input. Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. Analog column mux input. Analog column mux input. Analog column mux input Analog column mux input. Supply voltage. LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. Document Number: 38-12025 Rev. *M Page 10 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 32-Pin Part Pinout Figure 9. CY8C21634 32-Pin PSoC Device Figure 8. CY8C21434 32-Pin PSoC Device Figure 10. CY8C21434 32-Pin Sawn PSoC Device Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M Figure 11. CY8C21634 32-Pin Sawn PSoC Device Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M M, 12C SDA, P1[5] M, P1[3] M, 12C SCL, P1[1] Vss M, 12C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, 12C SCL, P1[7] 1 2 3 4 5 6 7 8 QFN (Top View) Document Number: 38-12025 Rev. *M M, 12C SDA, P1[5] M, P1[3] M, 12C SCL, P1[1] Vss M, 12C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, 12C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 QFN (Top View) 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES Page 11 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN**) Pin No. 1 2 3 4 5 6 6 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Digital IO IO IO IO IO IO Power IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power IO IO IO Power Type Analog I, M M M M M M Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] SMP P3[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Description Analog column mux input, integrating input. M M M M M M M M M M M M M M M I, M I, M I, M I, M I, M I, M I, M In CY8C21434 part. Switch Mode Pump (SMP) connection to required external components in CY8C21634 part. In CY8C21434 part. Ground connection in CY8C21634 part. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Ground connection. LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. Document Number: 38-12025 Rev. *M Page 12 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 12. CY8C21001 56-Pin PSoC Device Vss AI, P0[7] AI, P0[5] AI, P0[3] AI, P0[1] P2[7] P2[5] P2[3] P2[1] NC NC NC NC OCDE OCDO SMP Vss Vss P3[3] P3[1] NC NC I2C SCL, P1[7] I2C SDA, P1[5] NC P1[3] SCLK, I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6] P2[4] P2[2] P2[0] NC NC P3[2] P3[0] CCLK HCLK XRES NC NC NC NC NC NC P1[6] P1[4], EXTCLK P1[2] P1[0], I2C SDA, SDATA NC NC SSOP Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Type Digital Power IO IO IO IO IO IO IO IO Analog I I I I Pin Name Vss P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC NC NC OCDE OCDO SMP Vss Vss P3[3] Description Ground connection. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. I I OCD OCD Power Power Power IO Direct switched capacitor block input. Direct switched capacitor block input. No connection. No connection. No connection. No connection. OCD even data IO. OCD odd data output. Switch Mode Pump (SMP) connection to required external components. Ground connection. Ground connection. Document Number: 38-12025 Rev. *M Page 13 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued) Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 IO Type Digital Analog Pin Name P3[1] NC NC P1[7] P1[5] NC P1[3] P1[1] Vss NC NC P1[0] P1[2] P1[4] P1[6] NC NC NC NC NC NC XRES HCLK CCLK P3[0] P3[2] NC NC P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description IO IO IO IO Power IO IO IO IO No connection. No connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). No connection. IFMTEST. Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. No connection. No connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. VFMTEST. Optional External Clock Input (EXTCLK). No connection. No connection. No connection. No connection. No connection. No connection. Active high external reset with internal pull down. OCD high-speed clock output. OCD CPU clock output. Input OCD OCD IO IO No connection. No connection. IO IO IO IO IO IO IO IO Power I I I I I I Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. Document Number: 38-12025 Rev. *M Page 14 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Register Reference This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Mixed-Signal Array Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 8. Table 8. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Table 9. Register Map 0 Table: User Space Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Blank fields are Reserved and must not be accessed. PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F # Access is bit specific. ASE10CR0 RW RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF RW RW RW RW RW RW # RW # RW RW RW RW Document Number: 38-12025 Rev. *M Page 15 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 9. Register Map 0 Table: User Space (continued) Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name 20 # AMX_IN 21 W AMUXCFG 22 RW PWM_CR 23 # 24 # CMP_CR0 25 W 26 RW CMP_CR1 27 # 28 # ADC0_CR 29 W ADC1_CR 2A RW 2B # 2C # TMP_DR0 2D W TMP_DR1 2E RW TMP_DR2 2F # TMP_DR3 30 31 32 ACE00CR1 33 ACE00CR2 34 35 36 ACE01CR1 37 ACE01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and must not be accessed. DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW # RW # # RW RW RW RW RW RW RW RW A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 RW RW RW RW RW RW RW CPU_F DAC_D CPU_SCR1 CPU_SCR0 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RC W RW RW RL RW # # Table 10. Register Map 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 Blank fields are Reserved and must not be accessed. 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 80 RW 81 82 83 ASE11CR0 84 RW 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 # Access is bit specific. ASE10CR0 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 RW RW RW RW Document Number: 38-12025 Rev. *M Page 16 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 10. Register Map 1 Table: Configuration Space (continued) Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW CMP_GO_EN DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW DCB02IN 29 RW DCB02OU 2A RW 2B CLK_CR3 DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 30 31 32 ACE00CR1 33 ACE00CR2 34 35 36 ACE01CR1 37 ACE01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and must not be accessed. 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW D5 D6 D7 MUX_CR0 D8 MUX_CR1 D9 MUX_CR2 DA MUX_CR3 DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 ADC0_TR E5 ADC1_TR E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC DAC_CR FD CPU_SCR1 FE CPU_SCR0 FF RW RW RW RW RW RW RW RW RW RW RW R RW RW W W RW W RL RW RW # # Document Number: 38-12025 Rev. *M Page 17 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up to date electrical specifications, visit the web site http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC as specified, except where noted. Refer Table 25 on page 26 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 13. Voltage versus CPU Frequency 5.25 5.25 Figure 14. IMO Frequency Trim Options SLIMO Mode=1 4.75 Vdd Voltage 4.75 Vdd Voltage SLIMO Mode = 0 SLIMO Mode=0 lid g Va ratin n pe io O Reg 3.60 3.00 2.40 93 kHz 3 MHz 12 MHz CPU Frequency 24 MHz 3.00 SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 93 kHz 6 MHz 12 MHz 24 MHz 2.40 IMOFrequency Table 11 lists the units of measure that are used in this section. Table 11. Units of Measure Symbol oC dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 38-12025 Rev. *M Page 18 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Absolute Maximum Ratings Table 12. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Min -55 Typ 25 Max +100 Units oC Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC degrade reliability. TA Vdd VIO VIOZ IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss 0.5 Vss 0.5 -25 2000 - - - - - - - - +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200 oC V V V mA V mA Human Body Model ESD. Operating Temperature Table 13. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units oC oC Notes The temperature rise from ambient to junction is package specific. See Table 40 on page 38. The user must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 14. DC Chip-Level Specifications Symbol Vdd IDD Supply Voltage Supply Current, IMO = 24 MHz Description - Min 2.40 - 3 Typ 4 Max 5.25 Units V mA Notes See Table 23 on page 24. Conditions are Vdd = 5.0V, TA = 25oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. Conditions are Vdd = 2.55V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. IDD3 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.2 2 mA IDD27 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.1 1.5 mA Document Number: 38-12025 Rev. *M Page 19 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 14. DC Chip-Level Specifications (continued) Symbol ISB27 Description Sleep (Mode) Current with POR, LVD, Sleep - Timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) Current with POR, LVD, Sleep - Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Reference Voltage (Bandgap) Analog Ground 1.28 1.16 Min Typ 2.6 Max 4. Units A Notes Vdd = 2.55V, 0oC TA 40oC. Vdd = 3.3V, -40oC TA 85oC. Trimmed for appropriate Vdd. Vdd = 3.0V to 5.25V. Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. ISB VREF VREF27 AGND 2.8 1.30 1.30 5 1.32 1.33 A V V VREF VREF - 0.003 VREF V + 0.003 DC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 15. 5V and 3.3V DC GPIO Specifications Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Description 4 4 Vdd 1.0 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 V V mV nA pF pF Table 16. 2.7V DC GPIO Specifications Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Description 4 4 Vdd 0.4 - Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). Vdd = 2.4 to 3.0. Notes VOL Low Output Level - 0.75 V VIL Input Low Level - - 0.75 V Document Number: 38-12025 Rev. *M Page 20 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 16. 2.7V DC GPIO Specifications (continued) Symbol VIH VH IIL CIN COUT Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output Description - - - - Min 2.0 - 90 1 3.5 3.5 Typ - - - 10 10 Max Units V mV nA pF pF Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes Vdd = 2.4 to 3.0. DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 17. 5V DC Operational Amplifier Specifications Symbol VOSOA IEBOAa CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current - - - - 0.0 - - Min 10 200 4.5 - 80 10 Typ 2.5 15 - - 9.5 Vdd - 1 - 30 Max Units mV V/oC pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Notes TCVOSOA Average Input Offset Voltage Drift a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Table 18. 3.3V DC Operational Amplifier Specifications Symbol VOSOA IEBOAa CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current - - - - 0 - - Min 10 200 4.5 - 80 10 Typ 2.5 - - 9.5 Vdd - 1 - 30 Max 15 Units mV V/oC pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Notes TCVOSOA Average Input Offset Voltage Drift a.Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Table 19. 2.7V DC Operational Amplifier Specifications Symbol VOSOA IEBOAa CINOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) - - - - Min 10 200 4.5 Typ 2.5 - - 9.5 Max 15 Units mV V/oC pA pF Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Notes TCVOSOA Average Input Offset Voltage Drift Document Number: 38-12025 Rev. *M Page 21 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 19. 2.7V DC Operational Amplifier Specifications (continued) Symbol VCMOA GOLOA ISOA Open Loop Gain Amplifier Supply Current Description Common Mode Voltage Range 0 - - Min - 80 10 Typ - 30 Max Vdd - 1 V dB A Units Notes a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. DC Low Power Comparator Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 20. DC Low Power Comparator Specifications Symbol Description VREFLPC Low power comparator (LPC) reference voltage range ISLPC LPC supply current VOSLPC LPC voltage offset DC Switch Mode Pump Specifications Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 21. DC Switch Mode Pump (SMP) Specifications Symbol Description Min 4.75 Typ 5.0 Max 5.25 Units V Notes Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 2.55V. Configuration of footnote.a SMP trip voltage is set to 5.0V. SMP trip voltage is set to 3.25V. SMP trip voltage is set to 2.55V. Configuration of footnote.a SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 3.25V. Configuration of footnote.a SMP trip voltage is set to 2.55V. Configuration of footnote.a 0oC TA 100. 1.25V at TA = -40oC. Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 23 on page 24. Page 22 of 43 Min 0.2 - - Typ - 10 2.5 Max Vdd - 1 40 30 Units V A mV Notes VPUMP5V 5V Output Voltage from Pump VPUMP3V 3.3V Output Voltage from Pump 3.00 3.25 3.60 V VPUMP2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V IPUMP Available Output Current VBAT = 1.8V, VPUMP = 5.0V VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.3V, VPUMP = 2.55V Input Voltage Range from Battery Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump 5 8 8 1.8 1.0 1.0 1.2 - - - - - - - - 5 - - - 5.0 3.3 2.8 - - mA mA mA V V V V %VO VBAT5V VBAT3V VBAT2V VBATSTA RT Line VPUMP_ Line Regulation (over Vi range) Document Number: 38-12025 Rev. *M [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 21. DC Switch Mode Pump (SMP) Specifications (continued) Symbol Load Description - Min 5 Typ - Max Units %VO Notes Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 23 on page 24. Configuration of footnote.a Load is 5 mA. Configuration of footnote.a Load is 5 mA. SMP trip voltage is set to 3.25V. For I load = 1mA, VPUMP = 2.55V, VBAT = 1.3V, 10 uH inductor, 1 uF capacitor, and Schottky diode. VPUMP_ Load Regulation VPUMP_ Output Voltage Ripple (depends on cap/load) - Ripple 100 50 - - mVpp % E3 Efficiency 35 E2 Efficiency 35 80 - % FPUMP DCPUMP Switching Frequency Switching Duty Cycle - - 1.3 50 - - MHz % a. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 15. Figure 15. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT + SMP Battery PSoC Vss C1 Document Number: 38-12025 Rev. *M Page 23 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 DC Analog Mux Bus Specifications Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 22. DC Analog Mux Bus Specifications Symbol RSW RVDD Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to Vdd Min - - - - Typ Max 400 800 800 Units W W W Notes Vdd 2.7V 2.4V Vdd 2.7V DC POR and LVD Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 23. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 a. b. c. d. Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.36 2.82 4.55 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 Max 2.40 2.95 4.70 2.51a 2.99b 3.09 3.20 4.55 4.75 4.83 4.95 2.62c 3.09 3.16 3.32d 4.74 4.83 4.92 5.12 Units V V V V V V V V V V V V V V V V V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. - 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. Always greater than 50 mV above VLVD0. Always greater than 50 mV above VLVD3. Document Number: 38-12025 Rev. *M Page 24 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 DC Programming Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 24. DC Programming Specifications Symbol Description VddIWRITE Supply Voltage for Flash Write Operations IDDP Supply Current During Programming or Verify VILP Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)a FlashDR Flash Data Retention Min 2.70 - - 2.2 - - - Vdd 1.0 50,000 1,800, 000 10 Typ - 5 - - - - - - - - - Max - 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Units V mA V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). b For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 38-12025 Rev. *M Page 25 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 AC Electrical Characteristics AC Chip-Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 25. 5V and 3.3V AC Chip-Level Specifications Symbol FIMO24 Description Min Internal Main Oscillator Frequency for 24 MHz 23.4 Typ 24 Max Units a,b, MHz 24.6 c FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b, MHz c FCPU1 FCPU2 FBLK5 FBLK33 F32K1 Jitter32k Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency0(5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Peak-to-Peak Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time 0.93 0.93 0 0 15 - - 10 40 - 46.8 - - 0 24 12 48 24 32 100 1400 - 50 50 48.0 600 - - 24.6a,b MHz 12.3b,c MHz 49.2a,b, MHz d Notes Trimmed for 5V or 3.3V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications. 24.6b,d 64 200 - - 60 - 49.2a,c MHz kHz ns s % kHz MHz ps MHz s Trimmed. Using factory trim values. 12.3 - a. 4.75V < Vdd < 5.25V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. d. See the individual user module data sheets for information on maximum frequencies for user modules. Table 26. 2.7V AC Chip-Level Specifications Symbol FIMO12 Description Min Internal Main Oscillator Frequency for 12 MHz 11.5 Typ 120 Max Units a,b, MHz 12.7 c FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b, MHz c FCPU1 FBLK27 F32K1 CPU Frequency (2.7V Nominal) 0.093 Digital PSoC Block Frequency (2.7V Nominal) 0 Internal Low Speed Oscillator Frequency 8 3 12 32 3.15a,b MHz 12.5a,b, MHz c Notes Trimmed for 2.7V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 1. Trimmed for 2.7V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications. 96 kHz Document Number: 38-12025 Rev. *M Page 26 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 26. 2.7V AC Chip-Level Specifications (continued) Symbol Jitter32k Jitter32k TXRST FMAX TRAMP Description 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width Maximum frequency of signal on row input or row output. Supply Ramp Time Min - - 10 - 0 Typ 150 1400 - - - Max 200 - - 12.3 - Units ns s MHz s Notes a. 2.4V < Vdd < 3.0V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on maximum frequency for user modules. Figure 16. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Figure 17. 32 kHz Period Jitter (ILO) Timing Diagram Jitter32k F 32K1 AC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 27. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 7 7 Typ - - - 27 22 Max 12 18 18 - - Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Table 28. 2.7V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 6 6 18 18 Typ - - - 40 40 Max 3 50 50 120 120 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Document Number: 38-12025 Rev. *M Page 27 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Figure 18. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 29. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, 50 mV Overdrive Min Typ Max 100 200 Units ns ns Notes Vdd 3.0V. 2.4V < Vcc < 3.0V. AC Low Power Comparator Specifications Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 30. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min - - Typ Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC. AC Analog Mux Bus Specifications Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 31. AC Analog Mux Bus Specifications Symbol FSW Description Switch Rate - Min - Typ Max 3.17 Units MHz Notes Document Number: 38-12025 Rev. *M Page 28 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 32. 5V and 3.3V AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 20 50 50 - - - - - - - - - - 49.2 49.2 ns ns ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 50a - 50 - - - - - - - - Min Typ Max 49.2 24.6 - 49.2 24.6 - 49.2 24.6 Units MHz MHz ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. Maximum Frequency, With or Without Capture - Maximum Input Clock Frequency - - 24.6 MHz Maximum Input Clock Frequency Maximum Input Clock Frequency - - - - - - - - - - - - - 8.2 4.1 - 24.6 49.2 24.6 49.2 MHz MHz ns MHz MHz MHz MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. Width of SS_ Negated Between Transmissions 50 Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 38-12025 Rev. *M Page 29 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 33. 2.7V AC Digital Block Specifications Function All Functions Timer Counter Description Maximum Block Clocking Frequency Capture Pulse Width Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 20 100 100 - - - - - - - - - - 12.7 12.7 ns ns ns MHz MHz 100a 100 - - - - - - - Min Typ Max 12.7 - 12.7 - 12.7 12.7 Units MHz ns MHz ns MHz MHz Notes 2.4V < Vdd < 3.0V. Maximum Frequency, With or Without Capture - Maximum Input Clock Frequency - - 12.7 MHz Maximum Input Clock Frequency Maximum Input Clock Frequency - - - - - - - - - 6.35 4.1 - 12.7 12.7 MHz MHz ns MHz MHz Maximum data rate at 3.17 MHz due to 2 x over clocking. Width of SS_ Negated Between Transmissions 100 Transmitter Maximum Input Clock Frequency Receiver Maximum Input Clock Frequency Maximum data rate at 1.59 MHz due to 8 x over clocking. Maximum data rate at 1.59 MHz due to 8 x over clocking. a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 34. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description 0.093 20.6 20.6 150 Min - - - - Typ 24.6 5300 - - Max Units MHz ns ns s Document Number: 38-12025 Rev. *M Page 30 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 35. 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 - Typ Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - 24.6 MHz - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 41.7 41.7 150 - - - 5300 - - ns ns s Table 36. 2.7V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 - Typ Max 3.080 Units MHz Notes Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - 6.35 MHz - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 160 160 150 - - - 5300 - - ns ns s AC Programming Specifications Table 37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 37. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Min 1 1 40 40 0 - Typ - - - - - 15 Max 20 20 - - 8 - Units ns ns ns ns MHz ms Notes Document Number: 38-12025 Rev. *M Page 31 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 37. AC Programming Specifications (continued) Symbol TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min - - - - Typ 30 - - - Max - 45 50 70 Units ms ns ns ns Notes 3.6 < Vdd 3.0 Vdd 3.6 2.4 Vdd 3.0 AC I2C Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 38. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0V Symbol FSCLI2C THDSTAI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. 0 4.0 Standard Mode Min Max 100 - Min 0 0.6 Fast Mode Max 400 - Units kHz s s s s s ns s s ns TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - 1.3 0.6 0.6 0 100a 0.6 1.3 0 - - - - - - - 50 a. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Table 39. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C THDSTAI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set up Time for a Repeated START Condition Data Hold Time 0 4.0 Standard Mode Min Max 100 - Min - - Fast Mode Max - - Units kHz s s s s s TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C 4.7 4.0 4.7 0 - - - - - - - - - - - - Document Number: 38-12025 Rev. *M Page 32 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Table 39. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) (continued) Symbol TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Standard Mode Min Max Data Set-up Time 250 - Set up Time for STOP Condition 4.0 - Bus Free Time Between a STOP and START 4.7 - Condition Pulse Width of spikes are suppressed by the - - input filter. Description Fast Mode Min Max - - - - Units ns s s ns - - - - Figure 19. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Document Number: 38-12025 Rev. *M Page 33 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Packaging Information This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Packaging Dimensions Figure 20. 16-Pin (150-Mil) SOIC 8 1 PIN 1 ID DIMENSIONS IN INCHES[MM] MIN. REFERENCE JEDEC MS-012 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] MAX. PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] 0.061[1.549] 0.068[1.727] 0.050[1.270] BSC SEATING PLANE 0.010[0.254] X 45 0.016[0.406] 0.004[0.102] 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068 *B Figure 21. 20-Pin (210-MIL) SSOP 51-85077 *C Document Number: 38-12025 Rev. *M Page 34 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Figure 22. 28-Pin (210-Mil) SSOP 51-85079 *C Figure 23. 32-Pin (5x5 mm 0.93 MAX) QFN E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm) 51-85188 *B Document Number: 38-12025 Rev. *M Page 35 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Figure 24. 32-Pin (5x5 mm 0.60 MAX) QFN E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm) 001-06392 *A Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Figure 25. 32-Pin Sawn QFN Package TOP VIEW 4.90 5.10 PIN #1 CORNER N 1 2 0.20 DIA TYP. SIDE VIEW (0.93 MAX) 0.20 REF 0.230.05 BOTTOM VIEW 3.50 0.50 N 1 2 PIN #1 I.D. R0.20 0.45 4.90 5.10 SOLDERABLE EXPOSED 3.50 PAD 3.50 2X (0.05 MAX) SEATING PLANE 2X -0.20 3.50 NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD 001-30999 ** 2. BASED ON REF JEDEC # MO-248 Document Number: 38-12025 Rev. *M Page 36 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Figure 26. 32-Pin Thin Sawn QFN Package TOP VIEW 4.90 5.10 PIN #1 CORNER N 1 2 0.20 DIA TYP. 0.23 +/-0.05 SIDE VIEW BOTTOM VIEW 3.55 0.50 N 1 2 0.45 R0.30 R 4.90 5.10 3.55 SOLDERABLE EXPOSED PAD 3.5 2X (0.05 MAX) SEATING PLANE 2X -0.20 3.5 NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD 2. BASED ON REF JEDEC # MO-248 3. PACKAGE WEIGHT: 0.0388g 4. DIMENSIONS ARE IN MILLIMETERS [MIN/MAX] 5. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS. 6. PACKAGE CODE PART NO. LR32D LQ32D DESCRIPTION STANDARD PB-FREE 001-42168 *A Figure 27. 56-Pin (300-Mil) SSOP 51-85062 *C Document Number: 38-12025 Rev. *M Page 37 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Thermal Impedances Table 40. Thermal Impedances per Package Package 16 SOIC 20 SSOP 28 SSOP 32 QFN** 5x5 mm 0.60 MAX 32 QFN** 5x5 mm 0.93 MAX * TJ = TA + Power x JA Typical JA * 123 oC/W 117 oC/W 96 oC/W 27 oC/W 22 oC/W 55 oC/W 41 oC/W 39 oC/W 15 oC/W 12 oC/W Typical JC ** To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 41. Solder Reflow Peak Temperature Package 16 SOIC 20 SSOP 28 SSOP 32 QFN Minimum Peak Temperature* 240oC 240oC 240oC 240oC 260oC 260oC 260oC 260oC Maximum Peak Temperature *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 38-12025 Rev. *M Page 38 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C21x34 family. Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples Software PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Used by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers. PSoC ExpressTM As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. CY3210-ExpressDK PSoC Express Development Kit The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes: PSoC Express Software CD Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: Development Kits All development kits can be purchased from the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Document Number: 38-12025 Rev. *M Page 39 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes: CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Accessories (Emulation and Programming) Table 42. Emulation and Programming Accessories Part # CY8C21234-24S CY8C21334-24PVXI CY8C21434-24LFXI CY8C21534-24PVXI CY8C21634-24LFXI Pin Package 16 SOIC 20 SSOP 32 QFN 28 SSOP 32 QFN Flex-Pod Kita CY3250-21X34 CY3250-21X34 CY3250-21X34QFN CY3250-21X34 CY3250-21X34QFN Foot Kitb CY3250-16SOIC-FK CY3250-20SSOP-FK CY3250-32QFN-FK CY3250-28SSOP-FK CY3250-32QFN-FK Adapter Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. 3rd-Party Tools Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note AN2323 "Debugging - Build a PSoC Emulator into Your Board". Document Number: 38-12025 Rev. *M Page 40 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Ordering Information Switch Mode Pump Temperature Range XRES Pin No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes [+] Feedback Digital IO Pins Ordering Code Package 16 Pin (150-Mil) SOIC 16 Pin (150-Mil) SOIC (Tape and Reel) 20 Pin (210-Mil) SSOP 20 Pin (210-Mil) SSOP (Tape and Reel) 28 Pin (210-Mil) SSOP 28 Pin (210-Mil) SSOP (Tape and Reel) 32 Pin (5x5 mm 0.93 MAX) QFN b 32 Pin (5x5 mm 0.93 MAX) QFN b (Tape and Reel) 32 Pin (5x5 mm 0.60 MAX) QFN b 32 Pin (5x5 mm 0.60 MAX) QFN b (Tape and Reel) 32 Pin (5x5 mm 0.93 MAX) QFN b 32 Pin (5x5 mm 0.93 MAX) QFN b (Tape and Reel) 32 Pin (5x5 mm 0.93 MAX) SAWN QFN CY8C21234-24SXI CY8C21234-24SXIT CY8C21334-24PVXI 8K 8K 8K 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Yes Yes No No No No No No No No Yes Yes No No No No -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 12 12 16 16 24 24 28 28 28 28 26 26 28 28 28 28 12a 12a 16a 16a 24a 24a 28a 28a 28a 28a 26a 26a 28a 28a 28a 28a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CY8C21334-24PVXIT 8K CY8C21534-24PVXI 8K CY8C21534-24PVXIT 8K CY8C21434-24LFXI CY8C21434-24LFXIT CY8C21434-24LKXI CY8C21434-24LKXIT CY8C21634-24LFXI CY8C21634-24LFXIT CY8C21434-24LTXI 8K 8K 8K 8K 8K 8K 8K 8K 8K 32 Pin (5x5 mm 0.93 MAX) CY8C21434-24LTXIT SAWN QFN b (Tape and Reel) 32 Pin (5x5 mm 0.60 MAX) THIN SAWN QFN 32 Pin (5x5 mm 0.60 MAX) THIN SAWN QFN (Tape and Reel) 32 Pin (5x5 mm 0.93 MAX) SAWN QFN b CY8C21434-24LQXI CY8C21434-24LQXIT 8K CY8C21634-24LTXI 8K 8K 8K 512 512 512 Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C 4 4 4 4 4 4 26 26 26 26a 26a 26a 0 0 0 32 Pin (5x5 mm 0.93 MAX) CY8C21634-24LTXIT SAWN QFN b (Tape and Reel) 56 Pin OCD SSOP CY8C21001-24PVXI a. All Digital IO Pins also connect to the common analog mux. b. Refer to the section 32-Pin Part Pinout on page 11 for pin differences. Document Number: 38-12025 Rev. *M Page 41 of 43 Analog Outputs Analog Inputsa Flash (Bytes) SRAM (Bytes) Analog Blocks Digital Blocks CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Ordering Code Definitions CY 8 C 21 xxx-24xx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 38-12025 Rev. *M Page 42 of 43 [+] Feedback CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234 Document History Page Document Title: CY8C21234/CY8C21334/CY8C21434/CY8C21534/CY8C21634 PSoC(R) Mixed-Signal Array Document Number: 38-12025 Revision ** *A *B ECN 227340 235992 248572 Orig. of Change HMT SFV SFV Description of Change New silicon and document (Revision **). Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part. Revised the register mapping tables. Added a SSOP 28-pin part. Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534. Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634. Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs. Update PSoC Characteristics table. Update diagrams and specs. Final. Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table. DC Chip-Level Specification changes. Update links to new CY.com Portal. Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature. Update Electrical Specifications. Update Reflow Peak Temp. table. Add 32 MLF E-PAD dimensions. Add ThetaJC to Thermal Impedance table. Fix 20-pin package order number. Add CY logo. Update CY copyright. Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications. Clarify MLF thermal pad connection info. Replace 16-pin 300-MIL SOIC with correct 150-MIL. Update 32-pin QFN E-Pad dimensions and rev. *A. Update CY branding and QFN convention. Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram, CY8C21434-24LKXI. Update thermal resistance data. Add 56-pin SSOP on-chip debug non-production part, CY8C21001-24PVXI. Update typical and recommended Storage Temperature per industrial specs. Update copyright and trademarks. Add CapSense SNR requirement reference. Add new Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Update rev. of 32-Lead (5x5 mm 0.60 MAX) QFN package diagram. *C *D *E *F 277832 285293 301739 329104 HMT HMT HMT HMT *G *H *I *J 352736 390152 413404 430185 HMT HMT HMT HMT *K 677717 HMT *L *M 2147847 2273246 UVS/PYRS Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering information. UVS/AESA Added 32 pin thin sawn package diagram. (c) Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-12025 Rev. *M Revised April 18, 2008 Page 43 of 43 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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